In recent years, a non-volatile memory device in which stored data is not lost even if an external power supply is switched off has been actively developed. Here, until the 0.13 um generation, a size reduction of a flash memory has been mainly performed by reducing an area of a cell using a floating gate (FG) type or reducing a thickness of an insulating film.
However, after the 90 nm generation, because it has been difficult to reduce the thickness of the insulating film in the light of securing data retention characteristics, a trap type memory has been attracted which utilizes a trap in the insulating film as a charge storage layer.
Hereinafter, structures and operation methods of the trap memories proposed so far are schematically described making reference to drawings.
FIGS. 1A, 1B, 1C, and 1D are drawings illustrating a non-volatile memory device related to the present invention.
FIG. 1A shows a trap memory having the simplest planar type structure (this structure is related to the present invention, hereinafter, this type is represented by “related structure I”.). A laminated film 7 composed of a first insulating film 4, a charge storage layer 5 and a second insulating film 6 in this order is provided on a silicon substrate 1 and a memory gate electrode 8 is provided on the laminated film 7. On the both sides by which the memory gate electrode 8 is sandwiched in the silicon substrate 1, a source region 2 and a drain region 3 are formed so that the each region and the memory gate electrode 8 are partially overlapped.
In writing data, it is used that a channel hot electron, which is raised up a high energy state by a strong lateral electric field generated at a boundary of an inversion channel region 9 when a positive voltage is applied to the memory gate electrode 8 and the drain 3 as shown in FIG. 1B, is injected into the charge storage layer 5 in the laminated film 7.
On the other hand, in erasing data, the electron captured in the charge storage layer 5 is pulled out with a negative voltage applied to the memory gate electrode 8 by utilizing a Fowler-Nordheim (FN) type tunnel phenomenon. Or alternatively, by means of injecting into the charge storage layer 5 a band-to-band tunneling hot-hole which is generated by applying a positive voltage to the drain 3 in addition to applying a negative voltage to the memory gate electrode 8, the electron captured in the charge storage layer 5 is neutralized. Because a change in amount of electric charge stored in the charge storage layer 5 causes a change in the threshold value of the memory gate electrode 8, the information (data) on the amount of stored electric charge can be read out by using the change in the threshold value.
The related structure I shown in FIG. 1A has a problem that it is difficult to improve a writing efficiency. This is because a channel current flowing from the source to the drain increases by contraries due to the decrease in the resistance in a channel direction, when the channel hot electron becomes easy to be injected into the charge storage layer 5 by applying the high electric field to the memory gate electrode 8, whereby strengthening the vertical electric field from the gate crossing the charge storage layer 5 to the silicon substrate 1.
For this reason, the writing efficiency (a value obtained by dividing an amount of the channel hot electron injected into the charge storage layer per unit time by the channel current flowing from the source to the drain) does not increase, but decreases by contraries, even if the gate voltage is increased.
In order to solve the problem on the related structure I, a trap memory having a split gate type structure (hereinafter, this type is represented by “related structure II”.) is proposed.
As shown in FIG. 1C, the laminated film 7 composed of the first insulating film 4, the charge storage layer 5, and the second insulating film 6 in this order and the memory gate electrode 8 are provided on the silicon substrate 1. A word gate electrode 13 is arranged on insulating films 10 and 11 so as to contact with both one side of the memory gate electrode 8 and one of principal surfaces (upper surface in the figure) of the silicon substrate 1. On the both sides by which the gate electrodes 8 and 13 are sandwiched in the silicon substrate 1, the source region 2 and the drain region 3 are formed so that the source region 2 and the drain region 3 partially overlaps with the gate electrode 8, 13 respectively.
In writing the data, the strong lateral electric field generated at the boundary of the inversion channel region is utilized as well as the case of the simple planar structure (related structure I).
However, it is necessary that the injection of the electron is made easy by applying the strong vertical electric field to the memory gate 8 on the charge storage layer 5 and on the other hand, the channel current is kept not flowing excessively by increasing the resistance under the word gate 13 holding the voltage applied to the word gate 13 lower (FIG. 1D).
Because the vertical electric field crossing the charge storage layer 5 can be strengthened with suppressing the current flowing from the source to the drain, the electron can be injected into the charge storage layer 5 with higher efficiency by one or more orders than that of the related structure I.
Since the split gate structure is superior in writing efficiency for this reason, it is an important structure particularly for a logic LSI with a built-in memory which has large effect on chip cost reduction by reducing an area of a peripheral circuit.
In the trap memory having the split gate type structure (related structure II), there is another structure shown in FIG. 2A further improving the writing efficiency. As shown in FIG. 2A, it is a structure in which a dopant concentration in a portion contacting with the memory gate 8 under the word gate 13 is made high, and a low channel resistance region α (low threshold value region α) and a high channel resistance region β (high threshold value region β) are further produced in the channel under the word gate 8. This structure is represented by “related structure II′”.
FIG. 2A and FIG. 2B are views for illustrating an operation of a non-volatile memory device related to the present invention. Even if the channel currents for writing are made equal to each other, the region α has the lower resistance (FIG. 2B), a voltage drop from the source to the drain is the more highly concentrated in the high resistance channel region β near the memory gate 8. For that reason, the channel electron becomes easily accelerated (can easily become hot). Therefore, the writing efficiency in the related structure II′ is further improved than that of the related structure II.
In the split gate type structure (related structure II), the above-mentioned partially doped structure (related structure II′) has a merit improving the writing efficiency. On the other hand, when the writing operation is actually performed to memory cells arranged in an array, it has been observed that its disturbing resistance to an adjacent cell is deteriorated in comparison with that of the related structure II before it is improved.
Therefore, first, the disturbance is described by using FIG. 3 and FIG. 4, and then, a problem on the related structure II′ is described. The memory cells are arranged in an array (for example, 16×16 cells) so as to be efficiently arranged in a chip. FIGS. 3A, 3B, and 3C are views for illustrating a non-volatile memory device related to the present invention. FIGS. 4A and 4B are views for illustrating a characteristic of a non-volatile memory device related to the present invention. FIG. 4A shows a relationship between a time and a change in voltage of each cell, and FIG. 4B shows a relationship between a threshold value and a change in voltage of each cell.
When the voltage is applied to the cell for writing (FIG. 3A), the voltage is also applied to each electrode of an adjacent cell (unselected cell) through a common wiring as shown in FIG. 3B. Because the electron in the substrate is injected into the charge storage layer in the unselected cell by the stress caused by the external voltage, when the unselected cell is in an erased state in particular, an erasure level (a threshold value) increases and the memory window is narrowed (this is called a disturbance problem).
An arrangement of a voltage applied to the unselected cell can be categorized into three, that is, A, B, and C shown in FIG. 3B. It is assumed that the writing operation is performed to almost all the cells in the array of 16×16, for example. In this case, a time during which the stress is added (disturbing time: T_disturb) in each voltage arrangement is “writing time”×15 in the case of A and B, and “writing time”×15×15 in the case of C.
In case of the voltage arrangement A, the voltage difference between the source and the drain (V3−V2*) is small, and a voltage that is equal to or greater than the threshold value at which the inversion layer is formed is applied to the word gate (V13) and the memory gate (V8). Therefore, the electric field does not sharply decrease in the channel and the hot electron is scarcely generated. For this reason, the variation of the threshold value in the disturbing time is negligible small in the voltage arrangement A.
On the other hand, in case of the voltage arrangements B and C, the channel current does not flow by a negative voltage (this is called an inhibit voltage—Vinh) that is applied to the word gate. In contrast, there is a high electric field drop in the substrate under the word gate near the memory gate. For this reason, as shown in FIG. 3C, the hot electron is generated by a sub-threshold current such as a punch-through current or a band-to-band (between a valence band and a conduction band) tunneling current, and the electron flows into the charge storage layer 5. The sub-threshold current increases with the reduction in size of the memory cell, and the variation of the threshold value in the disturbing time becomes so large that it cannot be ignored with respect to a voltage stress of the voltage arrangements B and C (FIG. 4A).
The disturbance is described in detail in the case of the voltage arrangements B and C. A major factor in varying the threshold value of the cell in the voltage arrangement B is the punch-through current flowing inside the substrate. For this reason, as shown in FIG. 4B, when the negative inhibit voltage applied to the word gate is reduced, the variation of the threshold value of the cell in the voltage arrangement A increases.
On the other hand, in case of the voltage arrangement C, because the positive voltage (V2*) is applied to the source electrode, the punch-through current is smaller than that of the voltage arrangement B. However, because the disturbing time (T_disturb) is long, a phenomenon, that is, the hot electron generated by the band to band tunneling in the substrate under the word gate near the memory gate directly flows into the charge storage layer 5, cannot be ignored.
Accordingly, as shown in FIG. 4B, when the negative inhibit voltage applied to the word gate is increased, the variation of the threshold value of the cell in the voltage arrangement C increases. Because the dependence on the inhibit voltage for the variation of the threshold value in the voltage arrangement B is inverse relation to that in the voltage arrangement C, the inhibit voltage for writing is set so that a sum of the variation of the threshold value in the voltage arrangement B and that in the voltage arrangement C becomes a minimum. When this minimum value is used as an index of the disturbance resistance, the smaller this value is, the higher the disturbance resistance is.
In FIG. 5, the disturbance resistance of the related structure II′, whose writing efficiency is improved by increasing the channel doping concentration in the region β contacting with the laminated film in the word gate, is shown compared with that of the related structure II. In this figure, the horizontal axis represents the threshold value—Vinh, and the left and right vertical axes represent the change of voltage in each cell. Because the doping amount does not change near the source region or at the deep position in the substrate and whereby the reduction in punch-through current is limited, the variation of the threshold value in a stress voltage arrangement A of the related structure II′ is small, if any.
On the other hand, because the electric field strength in the substrate near the memory gate under the word gate increases due to the influence of the channel doping to the region β, the band-to-band tunneling current generated near the memory gate under the word gate increases considerably. For this reason, the variation of the threshold value in the stress voltage arrangement C enlarges widely. As shown in FIG. 5, the minimum value of the sum of the disturbance variation in a cell arrangement B and that in a cell arrangement C of the related structure II′ is increased in comparison with that of the related structure II (that is, the disturbance resistance is deteriorated).
Here, examples of the non-volatile memory devices are described in the patent documents 1 to 3.
A non-volatile semiconductor memory device described in the patent document 1 includes a floating gate formed on a silicon substrate with one conductivity type, an insulating film for covering this floating gate, a control gate formed so as to have an overlapped area on the floating gate with the insulating film interposed therebetween. Moreover, it is provided with a diffusion region with an opposite conductivity type formed on the surface of the silicon substrate adjacent to the floating gate and the control gate, and a metal wiring connected to the diffusion region on an interlayer insulating film. In this non-volatile semiconductor memory device, the metal wiring is formed with a silicide film on one surface of the diffusion region and the metal wiring is formed without a silicide film on the other surface of the diffusion region.
According to this non-volatile memory device, in a state in which an anti-silicidation film composed of an LPTEOS film is formed in a portion in which silicidation is not performed, a titanium film is formed, by means of forming a titanium film, and performing the silicidation by adding a heat treatment, the reaction between a base Si (source region) and the titanium film is supposed to be suppressed.
A split gate type non-volatile semiconductor memory device described in the patent document 2 includes a floating gate having an acute-angled portion formed from a side and an upper part, a control gate arranged so as to face the acute-angled portion, and an insulating region provided on the upper part of the floating gate, on a substrate respectively. In this split gate type non-volatile semiconductor memory device, the side corresponding to a control gate side among the sides of the insulating region inclines to a direction apart from the control gate using a normal direction on the substrate as a standard.
In the split gate type non-volatile memory, data erasure is performed by pulling out the electron from the floating gate to the control gate. According to the split gate type non-volatile semiconductor memory device described in the patent document 2, a non-volatile memory which can properly and stably perform the operation of data erasure, can be configured
A non-volatile semiconductor memory device described in the patent document 3 includes a floating gate formed on one conductivity type silicon substrate with a gate oxide film, a tunnel oxide film covering the floating gate, a control gate formed so that it overlaps with one end portion of the floating gate with a tunnel oxide film between them. And it includes an opposite conductivity type source/drain region formed on the surface of the semiconductor substrate adjacent to the floating gate and the control gate. In this device, a side wall insulating film is formed on only the portion which covers near the lower portion of the floating gate with the tunnel oxide film.
According to the non-volatile semiconductor memory device, a side wall insulating film is formed at the portion in which the tunnel oxide film covering the floating gate on the silicon substrate covers the vicinity of the lower portion of the floating gate. And the control gate is formed over the side wall insulating film so that one end portion of the floating gate and the control gate overlap. Therefore, a corner portion of the control gate does not enter a floating gate side sharply at a lower corner portion of the floating gate at which the reverse tunneling is likely to arise. Moreover, the interval between the control gate and the floating gate of which the word line is composed does not narrow, and the occurrence of the reverse tunneling failure can be suppressed.    Patent document 1: Japanese Patent Application Laid-Open No. 2000-228510    Patent document 2: Japanese Patent Application Laid-Open No. 2007-258572    Patent document 3: Japanese Patent Application Laid-Open No. Hei 11-284083